Senior SoC Design Engineer
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At Intel we take pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our company is directly linked to the growth and satisfaction of our employees. That is why Intel is committed to a work environment that is flexible and collaborative and allows our employees to reach their full potential.
Intel is a world leader in programmable logic solutions or FPGAs, enabling system designers and semiconductor companies to rapidly and cost effectively innovate, differentiate, and win in their markets. Intel combines the programmable logic technology originally invented in 1983 by Altera with software tools, intellectual property, and customer support to provide high-value programmable solutions to thousands of customers worldwide.
As a Senior SOC Design Engineer, you will be responsible for the micro-architecture and design of SoCs and related IPs within the SoC Design group handling hyperscale compute, configuration and security of programmable devices.
Most development happens pre-silicon and requires working closely with silicon design, firmware and validation teams for testing and support. During post silicon phase, engineer is expected to work with silicon validation team for productization. Experience with post silicon debugging experience is a plus.
As a senior member of the SOC-FPGA Configuration design team, you will be responsible for the micro-architecture, RTL design and/or integration of SoC components and IPs. Core responsibilities will include:
- Work with architects, software engineers, verification engineers and physical designers to define and implement the logic for our unique SOC-FPGA products, within a culture of industry standard best practices and methodologies.
- Designing and writing well-documented, high quality and synthesis-friendly RTL.
- Working with the Design Verification team to review test plans and assist in test failure debug.
- Support the post-silicon validation team to define validation strategies, test plans, quality reviews and assist with debug when necessary.
- Defining timing constraints and working with physical design engineers for design implementation.
- Working experience in integrating hyperscale computing cores in SoCs (x86, ARM, RISC-V, MIPS).
- Experience in implementing Security design systems with proven silicon implementations.
- Experience with performance analysis and integration of cache coherent and high-performance NOC architectures.
- Experience with clock planning, performance analysis and driving physical implementation of complex clocking and reset schemes.
Minimum Qualifications:
BS in Computer or Electrical Engineering or equivalent with 10+ years of experience or master's degree with 7 years of experience in memory technologies.
- Proven industry-track in writing and verifying complex RTL logic for SOC designs, preferably in Verilog or System Verilog.
- Experience working with verification engineers on simulation or emulation flows and familiarity with industry standard verification methodologies (UVM, Formal, Assertions, Cover points, IPXACT).
- Experience owning and debugging timing constraints, UPF, synthesis and driving IP quality checks and releases.
- Experience working with physical design engineers to assist with the implementation flow, eg, clock tree synthesis, floor planning and implementing ECO fixes.
- Analytical and communication skills and be able to work with and influence a globally distributed team.
- Experience with designing/integrating cryptographic, interface, storage and/or compression IPs will be a plus.
- Experience with cache coherent NOC, high speed peripherals and HW-SW programing interface is a plus.
- Experience in advanced low-power design techniques on SoC will be a plus.
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