Principal Fpga Design Engineer

APR Consulting Inc Pasadena, California
fpga design engineer design fpga electronics engineer nasa lead electrical digital sophisticated laboratory
December 11, 2022
APR Consulting Inc
Pasadena, California
A Principal FPGA Design Engineer position in Pasadena, CA recently opened up to support JPL/NASA. In this role you will lead the planning and execution of highly sophisticated and unique electronics systems with laboratory wide impact. To be considered for this role, you must have a Bachelor s degree in Electronics, Electrical, or Computer Engineering or related discipline with typically a minimum of 9 years of related experience. You must also be a US Citizen or Permanent Resident.Location: Pasadena, CA 91109Position: Electrical Engineer IVPay Rate: $88.74/hr+ DOEDuration: 24 monthsFlexible work schedule: 9/80We do offer PTO, holidays, 401k, medical, dental, and visionResponsibilities:As a principal level FPGA Design Engineer, you will lead the planning and execution of highly sophisticated and unique electronics systems with Laboratory wide impact.ESSENTIAL DUTIES AND RESPONSIBILITIES Include the following. Other duties may be assigned:Lead, design, and deliver a verified fight qualified FPGAImprove FPGA design flowImprove hardware resilience techniquesApply digital design knowledge and principles to extremely complex designsMentor junior engineersRequirements:Bachelor s degree in Electronics, Electrical, or Computer Engineering or related discipline with typically a minimum of 9 years of related experience; Master s in similar disciplines with a minimum of 7 years of related experience; or PhD in similar disciplines with a minimum of 5 years of related experienceExpert in architecting, designing, implementing, and testing advanced digital systemsFluent coding in Verilog and System VerilogExtensive experience crafting FPGAs and embedded processors designs using tools: Synplify Pro/Premier, Xilinx Vivado, Microsemi Libero SoC, and Mentor Graphics Questa design suiteDemonstrated experience leading team and presenting in design reviewsMust be successful leading FPGA/ASIC designs through full life cycle from initial concept to burn review.Success infusing new design/verification technologies and methodologiesSkillfully handles fast pace and dynamic product development environmentOutstanding leader able to build consensus as well as excellent written/verbal communication skillsDesired Skills:Experience designing with radiation tolerant Xilinx and Microsemi FPGAsExperience in bus standards protocol such as: SpaceWire, PCI, MILSTD-1553, CAN, and EthernetEmbedded Software knowledge and experienceSystemC or C++, MatlabExperience with digital twin modelingFamiliar with Failure Analysis and worst-case analysisAt a minimum, a 7-year background check, education verification, employment verification, and drug screen will be conducted upon hire. Your suitability for employment is contingent upon successfully passing these required pre-employment screenings.About our client:Our client is a research and development lab federally funded by NASA and managed by Caltech. Manages many of NASA's robotic missions exploring Earth, the solar system, and our universe.This particular client is requiring that all new hires show proof of vaccination. However, accommodations may be made for those with disabilities or religious reasons who cannot obtain a vaccine.About APR:Since 1980 APR Consulting, Inc. has provided professional recruiting and contingent workforce solutions to a diverse mix of clients, industries, and skill sets nationwide.We are an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law.Don't miss out on this amazing opportunity! If you feel your experience is a match for this position, please apply today and join our team. We look forward to working with you!#SPC1

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