Remote Design Verification Engineer
Jobot
Remote
remote
design
engineer
engineering
technical
ip development
team
training
systemverilog
uvm
c++
remote
design
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September 26, 2022
Jobot
Garland, TX
Remote Design Verification Engineers
Why join us?
Why join us?
- Full-time permanent employee with competitive salary.
- 20 days paid vacation and observed holidays.
- 401k Matching up to 6%.
- Medical, dental, vision, term life, AD&D, and disability (100% of all premiums covered by the Company).
- Eligibility for bonuses.
- Birthday gifts.
- Book budget.
- Leading industry career and personal development training.
- BSc/MSc in Electronic Engineering, Computer Engineering, or Computer Science.
- 7 years of project-proven verification experience.
- Experienced SystemVerilog/UVM developer
- Block and integration-level
- Coverage-driven, self-checking verification environments from scratch
- High-level sequence-based stimulus
- Complex transaction-based checkers (e.g. scoreboards with data translation and ordering)
- Register models
- Specification level checks for several different protocols, e.g. AXI, DDRx, PCIe, USBx.
- Requirements capture and traceability
- Estimation, prioritizing
- Metrics used to determine verification closure
- Ownership of work, from planning to implementation.
- Experience dealing directly with strict deadlines and technical challenges.
- Effective communication and collaboration with others.
- Specman/e expertise to a similar level.
- C/C++ developing, or integrating, reference models into SystemVerilog/UVM environments.
- Experience leading a technical team, including mentoring, training, and performing technical peer reviews.
- Embedded programming for ARM, or GPU processors.
- Python or Perl.
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